The panel display device, such as the Liquid Crystal Display (LCD) and the Organic Light Emitting Display (OLED) comprises a plurality of pixels aligned in array. Each pixel generally comprises sub pixels of red, green, blue, three colors. Each sub pixel is controlled by one gate line and one data line. The gate line is employed to control the on and off of the sub pixel, and the data line applies various data voltage signals to make the sub pixel show various gray scales, and thus for realizing the full color image display.
With the development of the display technology, the requirements of the people to the display qualities of the display device, such as the display brightness, the color reduction, the richness of the image color gets higher and higher. The display merely utilizing the red, green and blue, three primary colors can no longer satisfy the requirements of the people to the display device. Thereafter, the four colors display device having red, green, blue, white four colors is proposed. One white sub pixel is added in each pixel for forming the RGBW pixel structure constructed by the red sub pixel R, the green sub pixel G, the blue sub pixel B and the white sub pixel W. In the same display image, the display device utilizing the RGBW pixel structure has the larger pixel pitch than the display device utilizing the RGB three colors sub pixels structure, and the added white sub pixel has high transmission rate. The RGBW four colors sub pixels structure display device has benefits of high transmission rate and high aperture ratio, and is pursued by the consumers.
FIG. 1 shows a demultiplex type display driving circuit used in a RGBW four colors pixel structure display device according to prior art, comprising: a plurality of driving units, and each driving unit comprises: eight data lines D1-D8, which are mutually parallel, sequentially aligned and vertical, at least two scan lines Gn (n is a positive integer), which are mutually parallel, sequentially aligned and horizontal, sub pixels 100 of at least two rows-eight columns, and sixteen in total, which are aligned in array, and first and second demultiplex modules De10, De20; each sub pixel 100 is electrically coupled to the scan line corresponded with the row where the sub pixel 100 is and the data line corresponded with the column where the sub pixel 100 is; each demultiplex module comprises four thin film transistors, and gates of the four thin film transistors are electrically coupled to a first branch control signal Demux1, a second branch control signal Demux2, a third branch control signal Demux3 and a fourth branch control signal Demux4 respectively, and sources are all electrically coupled to the same data signal, and sources are electrically coupled to one data line, respectively. Specifically, the first demultiplex module De10 comprises: a first thin film transistor T10, and a gate of the first thin film transistor T10 is electrically coupled to the first branch control signal Demux1, and a source is electrically coupled to a first data signal Data10, and a drain is electrically coupled to a first data line D1; a second thin film transistor T20, and a gate of the second thin film transistor T20 is electrically coupled to the second branch control signal Demux2, and a source is electrically coupled to the first data signal Data10, and a drain is electrically coupled to a sixth data line D6; and a third thin film transistor T30, and a gate of the third thin film transistor T30 is electrically coupled to the third branch control signal Demux3, and a source is electrically coupled to a first data signal Data10, and a drain is electrically coupled to a seventh data line D7; a fourth thin film transistor T40, and a gate of the fourth thin film transistor T40 is electrically coupled to the fourth branch control signal Demux4, and a source is electrically coupled to the first data signal Data10, and a drain is electrically coupled to a fourth data line D4; the second demultiplex module De20 comprises: a fifth thin film transistor T50, and a gate of the fifth thin film transistor T50 is electrically coupled to the first branch control signal Demux1, and a source is electrically coupled to the second data signal Data20, and a drain is electrically coupled to a fifth data line D5; and a sixth thin film transistor T60, and a gate of the sixth thin film transistor T60 is electrically coupled to the second branch control signal Demux2, and a source is electrically coupled to a second data signal Data20, and a drain is electrically coupled to a second data line D2; a seventh thin film transistor T70, and a gate of the seventh thin film transistor T70 is electrically coupled to the third branch control signal Demux3, and a source is electrically coupled to a second data signal Data20, and a drain is electrically coupled to a third data line D3; an eighth thin film transistor T80, and a gate of the eighth thin film transistor T80 is electrically coupled to the fourth branch control signal Demux4, and a source is electrically coupled to the second data signal Data20, and a drain is electrically coupled to an eighth data line D8. The first data signal Data10 have a positive polarity, and the second data signal Data2 have a negative polarity, and the gate line Gn receives the scan signal Gate, and pulse durations of the first, second, third and fourth branch control signals Demux1, Demux2, Demux3, Demux4 are ¼ of a pulse duration of the scan signal Gate.
Please refer to FIG. 2. With the constantly increase of the resolution of the display device, the pulse duration of the scan signal Gate also has been constantly shortened. The pulse durations of the first, second, third and fourth branch control signals Demux1, Demux2, Demux3, Demux4 are constantly compressed. Then, the data switch time arranged for the sub pixels of each column is shortened, too. Consequently, the charging rate of the sub pixel is insufficient, and the data signal entering the sub pixel cannot reach the voltage level.